1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method for semiconductor metrology.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender nonoptimal control of critical processing parameters, such as throughput accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an ideal monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
Among the parameters it would be useful to monitor and control are critical dimensions (CDs), which are the smallest feature sizes that particular processing devices may be capable of producing. For example, the minimum widths w of polycrystalline (polysilicon or poly) gate lines for metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors) may correspond to one CD for a semiconductor device having such transistors. Similarly, the pitch p (distance between centers of parallel gate lines, for example) may be another CD for a semiconductor device having such transistors arranged in a dense array.
However, measurement noise limits the ability to control precisely CDs in semiconductor and microelectronic device manufacturing. Typically, to obtain a good estimate of a CD in the presence of such measurement noise, multiple measurements of poly gate lines of many different MOS transistors, for example, must be made and a suitable average and/or median of these multiple measurements may then be used to estimate the xe2x80x9ctrue valuexe2x80x9d of the CD. However, measuring the poly gate lines of many different MOS transistors is time consuming and costly in terms of metrology tool utilization. For example, a conventional implementation of multiple measurement metrology using an on-line scanning electron microscope (SEM) takes measurements of a representative type of line at many different sites on a die and/or wafer, each site requiring a time-consuming separate alignment and/or stage travel of the SEM.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided for manufacturing, the method including processing a workpiece in a processing step, measuring a critical dimension of features formed on the workpiece using a test structure formed on the workpiece, the test structure including a plurality of the features, and forming an output signal corresponding to the critical dimension measurements. The method also includes feeding back a control signal based on the output signal to adjust the processing performed in the processing step if the output signal corresponding to the critical dimension measurements indicates a predetermined tolerance value has been exceeded.